Apache Slashes SoC Design Time and Improves Chip Yield with New Vectorless Dynamic -TM- Power Technology
RedHawk-SDL Features Breakthrough Dynamic Voltage Drop Analysis for
Simultaneous Switching, On-Chip Inductance and Decoupling Capacitance
Analysis
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--April 14, 2003--
Apache Design Solutions, the technology leader in physical design
integrity solutions for system-on-chip (SoC) designs, today announced
RedHawk-SDL, a full-chip cell-based power-ground design and
verification solution with integrated transistor-level
characterization for assured accuracy. RedHawk-SDL is in use today by
early adopters in the U.S. and Japan on advanced 90nm and 130nm
production SoC projects.
Dynamic power issues are a growing cause of re-spins in 130nm
designs, and the problems increase with the move to 90nm and 65nm
processes due to their lower voltage supplies, higher frequencies,
run-away complexity and advanced power management requirements. Even
180nm designs are subject to simultaneous switching failures.
RedHawk-SDL (Static, Dynamic and L inductance) analyzes the
effects of on-chip and off-chip (package) inductance, simultaneous
switching (core, memory and I/O), decoupling capacitance (intrinsic
and intentional), and dynamic voltage drop impact on clock skew and
timing. RedHawk-SDL's comprehensive power methodology provides early
feedback and decreases the likelihood of a chip re-spin while
improving yields.
By using RedHawk-SDL, SoC designers can rapidly analyze dynamic
voltage waveforms at every instance on the full-chip power grid early
in the design process, protect these areas with optimal decoupling
capacitance, and verify the full-chip power integrity. The
single-kernel architecture offers dramatic speed-up and ease-of-use,
enabling a viable "what-if" methodology during design and analysis.
RedHawk-SDL's full-chip runtime, from design input to final
results display, is roughly two hours for four million gates (single
CPU). This includes power calculation, power-grid RLC extraction,
static IR/EM, transient voltage drop simulation, and decoupling
capacitance analysis. This means the full-chip dynamic run of a
high-end 20-million gate SoC can be completed overnight -- much faster
than current static-only solutions.
"Power has become the number one problem for design engineers,"
said Gary Smith, chief analyst for EDA in Gartner Dataquest's Design
and Engineering Group, in the October 2002 Market Trends report.
"Power analysis is growing. It will take a while for the industry to
catch up with all of the power related problems facing engineers
today."
RedHawk-SDL addresses these power-related challenges. Smith
expects the power analysis market to grow over 30 percent in the next
two years.
RedHawk-SDL embodies many breakthrough patent-pending technologies
that address these challenges for the first time in an easy-to-use
product:
|
| -- | Single-kernel hierarchical engine supporting power analysis,
RLC network extraction, reduction and transient simulation
|
| -- | Cell-level power calculation with proprietary AccuPower(TM)
engine
|
| -- | On-chip power/ground extraction, including self and mutual
inductance, based on effective-loop analysis
|
| -- | Vectorless Dynamic(TM) switching analysis driven by static
timing and embedded logic simulation, instead of user-provided
vectors
|
| -- | Decoupling capacitance analysis and optimization
|
| -- | High-capacity NSPICE simulation of inductance-dominated linear
and non-linear mesh networks
|
| -- | Waveform-based Apache Power Library (APL) cell and memory
macrocell characterization for dynamic analysis
|
"We purchased Apache's RedHawk-SDL to precisely pinpoint dynamic
hot spots that we have never before been able to see with traditional
static analysis tools or block-based dynamic solutions," said Hiroyuki
Tsujikawa, manager of EDA technology design group at Matsushita
Electric Industrial Co. Ltd. in Japan. "The early power grid design
feedback we get from RedHawk-SDL includes the inductive effects and
decoupling capacitance, which enables us to optimize power-grid
decisions before we get to final verification. The vectorless approach
gives us a painless way to identify the worst-case dynamic hot spots,
since it is impossible to capture such a vector set on a full-chip SoC
design."
RedHawk-SDL's Vectorless Transient Methodology
Existing methodologies use a combination of gate-level static IR
drop tools, and vector-driven transistor-level dynamic tools usable
only on blocks. Static solutions do not consider inductive and
capacitive effects, and vector-based dynamic solutions are impractical
for full-chip analysis. Also, the current ad hoc approach to placing
de-coupling capacitance to control dynamic effects limits a designer's
ability to confidently resolve noise problems during design.
Since power is a full-chip issue and the complexity of dynamic
analysis is one to two orders of magnitude greater than that of static
analysis, existing multi-kernel tools with disparate databases do not
provide a viable, single platform for full-chip dynamic voltage drop
analysis and verification.
RedHawk-SDL's Vectorless Dynamic technology enables designers, for
the first time, to accurately analyze the impact of package
parasitics, on-chip inductance, and decoupling capacitance on
transient hot spots. Recent pseudo-dynamic approaches attempt to
approximate instantaneous behavior by performing multiple successive
static analyses within a clock cycle, ignoring inductance and
decoupling capacitance effects. By contrast, RedHawk-SDL performs true
full-chip transient simulation considering all power-ground RLC
parasitics, as well as the SPICE current waveforms for each cell from
APL, yielding accurate voltage drop waveforms at each cell instance.
The instance-based dynamic waveforms facilitate accurate analysis of
the dynamic impact to chip timing, and the ability to determine the
precise amount and location of decoupling capacitance needed.
The NSPICE engine embedded in RedHawk-SDL enables another critical
first-time capability. Designers can now perform a detailed skew
analysis of the entire clock tree, including full-chip dynamic
power-grid effects and switching current modeling of logical elements,
with SPICE-level accuracy.
"The need for full-chip dynamic power analysis is critical for
many 130nm, 90nm and upcoming 65nm designs," said Keith Mueller,
Apache vice president of sales and marketing. "Our extensive
experience with early top-tier IC companies on yield-critical
production projects has validated RedHawk's methodology, accuracy and
value in nanometer flows."
Pricing and Availability
RedHawk-SDL is scheduled for production release in Q3 2003.
RedHawk-SDL is licensed on Linux, Sun Solaris and HP-UX. Annual
license pricing varies with configuration and starts at $160,000.
About Apache Design Solutions
Apache is a provider of innovative next-generation physical design
integrity software that accelerates the design process and guarantees
the reliability of massive system-on-chip semiconductors operating at
gigahertz frequencies. By providing tools for power, timing and system
I/O integrity, Apache enables leading networking, wireless,
communication, consumer and semiconductor companies to develop highly
competitive and reliable products. Apache's physical design integrity
products are used early in the sub-130 nanometer design process with
minimal setup, delivering the highest standards of computational
performance, capacity handling and integrity. For more information,
including a white paper on dynamic analysis, visit www.apache-da.com.
Apache Design Solutions, NSPICE, RedHawk-SDL and Vectorless
Dynamic are trademarks of Apache Design Solutions Inc.
CONTACT: Apache Design Solutions Inc.
Keith Mueller, 650/237-5415
keith@apache-da.com
or
Public Relations for Apache
Cayenne Communication
Michelle Clancy, 252/940-0981
michelle.clancy@cayennecom.com
